diff options
| author | Vineet Gupta <vgupta@synopsys.com> | 2013-09-05 13:17:49 +0530 |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2013-11-06 10:41:37 +0530 |
| commit | 63d2dfdbf4b12a6993adf5005fd308d611d453d6 (patch) | |
| tree | b4878a30a70b513ff081f2a4ec0f61a683d0e029 /arch/arc/include/asm/cache.h | |
| parent | f3e4de327403cee6f76c0dca1b45d6fb0b08daf4 (diff) | |
ARC: cacheflush refactor #2: I and D caches lines to have same size
Having them be different seems an obscure configuration.
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/include/asm/cache.h')
| -rw-r--r-- | arch/arc/include/asm/cache.h | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h index e4abdaac6f9f..2fd3162ec4df 100644 --- a/arch/arc/include/asm/cache.h +++ b/arch/arc/include/asm/cache.h @@ -17,13 +17,7 @@ #endif #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) - -/* For a rare case where customers have differently config I/D */ -#define ARC_ICACHE_LINE_LEN L1_CACHE_BYTES -#define ARC_DCACHE_LINE_LEN L1_CACHE_BYTES - -#define ICACHE_LINE_MASK (~(ARC_ICACHE_LINE_LEN - 1)) -#define DCACHE_LINE_MASK (~(ARC_DCACHE_LINE_LEN - 1)) +#define CACHE_LINE_MASK (~(L1_CACHE_BYTES - 1)) /* * ARC700 doesn't cache any access in top 256M. |