diff options
| author | Srikanth Thokala <srikanth.thokala@intel.com> | 2021-08-06 02:40:10 +0530 |
|---|---|---|
| committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2021-08-20 13:47:05 +0100 |
| commit | 0c87f90b4c13586a00fbe63524c7be197609d8dc (patch) | |
| tree | 71f7482c3bef2828edbcdbe7b0870856d27977b3 /MAINTAINERS | |
| parent | 33d2f8e4ffd144a0b0c9968558820af0164a2d53 (diff) | |
PCI: keembay: Add support for Intel Keem Bay
Add driver for Intel Keem Bay SoC PCIe controller. This controller
is based on DesignWare PCIe core.
In Root Complex mode, only internal reference clock is possible for
Keem Bay A0. For Keem Bay B0, external reference clock can be used
and will be the default configuration. Currently, keembay_pcie_of_data
structure has one member. It will be expanded later to handle this
difference.
Endpoint mode link initialization is handled by the boot firmware.
Link: https://lore.kernel.org/r/20210805211010.29484-3-srikanth.thokala@intel.com
Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
Signed-off-by: Srikanth Thokala <srikanth.thokala@intel.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Diffstat (limited to 'MAINTAINERS')
| -rw-r--r-- | MAINTAINERS | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index a61f4f3b78a9..23e614e9c669 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14422,6 +14422,13 @@ S: Maintained F: Documentation/devicetree/bindings/pci/hisilicon-histb-pcie.txt F: drivers/pci/controller/dwc/pcie-histb.c +PCIE DRIVER FOR INTEL KEEM BAY +M: Srikanth Thokala <srikanth.thokala@intel.com> +L: linux-pci@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/pci/intel,keembay-pcie* +F: drivers/pci/controller/dwc/pcie-keembay.c + PCIE DRIVER FOR MEDIATEK M: Ryder Lee <ryder.lee@mediatek.com> M: Jianjun Wang <jianjun.wang@mediatek.com> |