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authorAlison Schofield <alison.schofield@intel.com>2022-10-27 19:56:50 +0200
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2022-10-28 17:28:23 +0200
commitf350c68e3cd5ce605e44c7830029cd936a223f66 (patch)
tree65a50adf7ed8caae31ebc459b1a8b3b584dc9c08 /Kconfig
parent183f0a09d32cf4f007f52718becf1b963549cb54 (diff)
ACPICA: Add CXL 3.0 structures (CXIMS & RDPAS) to the CEDT table
ACPICA commit 2d8dc0383d3c908389053afbdc329bbd52f009ce The CXL 3.0 Specification [1] adds two new structures to the CXL Early Discovery Table (CEDT). The CEDT may include zero or more entries of these types: CXIMS: CXL XOR Interleave Math Structure Enables the host to find a targets position in an Interleave Target List when XOR Math is used. RDPAS: RCEC Downstream Post Association Structure Enables the host to locate the Downstream Port(s) that report errors to a given Root Complex Event Collector (RCEC). Link: https://www.computeexpresslink.org/spec-landing # [1] Link: https://github.com/acpica/acpica/commit/2d8dc038 Signed-off-by: Alison Schofield <alison.schofield@intel.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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