diff options
| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2021-03-11 18:22:34 +0100 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2021-03-12 12:29:11 -0800 |
| commit | bfdfe7fc1bf9e8c16e4254236c3c731bfea6bdc5 (patch) | |
| tree | e133236517c97a32f4868e1b874a766bd53f22c2 /Documentation | |
| parent | 5215206d8b1574c4ba8915a61fe841c376d51ed2 (diff) | |
docs: networking: phy: Improve placement of parenthesis
"either" is outside the parentheses, so the matching "or" should be too.
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/networking/phy.rst | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/networking/phy.rst b/Documentation/networking/phy.rst index 06adfc2afcf0..3f05d50ecd6e 100644 --- a/Documentation/networking/phy.rst +++ b/Documentation/networking/phy.rst @@ -80,8 +80,8 @@ values of phy_interface_t must be understood from the perspective of the PHY device itself, leading to the following: * PHY_INTERFACE_MODE_RGMII: the PHY is not responsible for inserting any - internal delay by itself, it assumes that either the Ethernet MAC (if capable - or the PCB traces) insert the correct 1.5-2ns delay + internal delay by itself, it assumes that either the Ethernet MAC (if capable) + or the PCB traces insert the correct 1.5-2ns delay * PHY_INTERFACE_MODE_RGMII_TXID: the PHY should insert an internal delay for the transmit data lines (TXD[3:0]) processed by the PHY device |