diff options
| author | James Morse <james.morse@arm.com> | 2019-06-07 16:14:06 +0100 |
|---|---|---|
| committer | Jonathan Corbet <corbet@lwn.net> | 2019-06-20 14:16:00 -0600 |
| commit | eb8ed28f024fe428a08ee6b7c4de6a31ff6610ad (patch) | |
| tree | 31399241f2fabb9368df975e2189cf57f7210bbb /Documentation | |
| parent | 22aac857394c6105803afcb9801e4e4771eb755d (diff) | |
Documentation: x86: Contiguous cbm isn't all X86
Since commit 4d05bf71f157 ("x86/resctrl: Introduce AMD QOS feature")
resctrl has supported non-contiguous cache bit masks. The interface
for this is currently try-it-and-see.
Update the documentation to say Intel CPUs have this requirement,
instead of X86.
Cc: Babu Moger <Babu.Moger@amd.com>
Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/x86/resctrl_ui.rst | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/x86/resctrl_ui.rst b/Documentation/x86/resctrl_ui.rst index 225cfd4daaee..066f94e53418 100644 --- a/Documentation/x86/resctrl_ui.rst +++ b/Documentation/x86/resctrl_ui.rst @@ -342,7 +342,7 @@ For cache resources we describe the portion of the cache that is available for allocation using a bitmask. The maximum value of the mask is defined by each cpu model (and may be different for different cache levels). It is found using CPUID, but is also provided in the "info" directory of -the resctrl file system in "info/{resource}/cbm_mask". X86 hardware +the resctrl file system in "info/{resource}/cbm_mask". Intel hardware requires that these masks have all the '1' bits in a contiguous block. So 0x3, 0x6 and 0xC are legal 4-bit masks with two bits set, but 0x5, 0x9 and 0xA are not. On a system with a 20-bit mask each bit represents 5% |