diff options
| author | Xianglong Du <Xianglong.Du@csr.com> | 2013-10-02 08:13:49 +0800 |
|---|---|---|
| committer | Wim Van Sebroeck <wim@iguana.be> | 2013-11-17 19:37:23 +0100 |
| commit | f0fcbdbf202e2be36c8eb6d1f5c01f95805777de (patch) | |
| tree | 775898deec716feca6e7d2742405e754679eddc7 /Documentation | |
| parent | 85eee81922399ec0be1b2c870f9333b4bca56650 (diff) | |
watchdog: sirf: add watchdog driver of CSR SiRFprimaII and SiRFatlasVI
On CSR SiRFprimaII and SiRFatlasVI, the 6th timer can act as a watchdog
timer when the Watchdog mode is enabled.
watchdog occur when TIMER watchdog counter matches the value software
pre-set, when this event occurs, the effect is the same as the system
software reset.
Signed-off-by: Xianglong Du <Xianglong.Du@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Cc: Romain Izard <romain.izard.pro@gmail.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/watchdog/sirfsoc_wdt.txt | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/watchdog/sirfsoc_wdt.txt b/Documentation/devicetree/bindings/watchdog/sirfsoc_wdt.txt new file mode 100644 index 000000000000..9cbc76c89b2b --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/sirfsoc_wdt.txt @@ -0,0 +1,14 @@ +SiRFSoC Timer and Watchdog Timer(WDT) Controller + +Required properties: +- compatible: "sirf,prima2-tick" +- reg: Address range of tick timer/WDT register set +- interrupts: interrupt number to the cpu + +Example: + +timer@b0020000 { + compatible = "sirf,prima2-tick"; + reg = <0xb0020000 0x1000>; + interrupts = <0>; +}; |