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authorEugen Hristev <eugen.hristev@microchip.com>2019-09-11 06:39:20 +0000
committerStephen Boyd <sboyd@kernel.org>2019-09-17 22:00:31 -0700
commit81a6b601f9f49be4e5972c351ad27cb13265c225 (patch)
tree44558897d1ce28c7fac4841f2d059dced7cdfee9 /Documentation
parent69a6bcde7fd3fe6f3268ce26f31d9d9378384c98 (diff)
clk: at91: allow 24 Mhz clock as input for PLL
The PLL input range needs to be able to allow 24 Mhz crystal as input Update the range accordingly in plla characteristics struct Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Link: https://lkml.kernel.org/r/1568183622-7858-1-git-send-email-eugen.hristev@microchip.com Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Fixes: c561e41ce4d2 ("clk: at91: add sama5d2 PMC driver") Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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