diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2016-12-13 15:38:37 -0800 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2016-12-13 15:38:37 -0800 |
commit | bb3dd056ed1af9b186f0d9fe849eab78c51d14ce (patch) | |
tree | ba5c44647d2ee786426d53c446a99dcecd64e9fb /Documentation | |
parent | 7b882cb800095f216c9da6b6735d10d26df8168b (diff) | |
parent | fafd67940774733fa97f4b09412aea6981b82e0a (diff) |
Merge tag 'spi-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi updates from Mark Brown:
"The nicest things about this release for me is seeing some older
drivers getting some cleanups and modernization, it's really good to
see things moving forwards even for older drivers.
In content terms it's a fairly humdrum release but where the work has
been happening is great.
- Support for simultaneous use of internal and GPIO chip selects for
devices that require the use of the internal select even if it's
not connected and a GPIO is actually routed to the slave device.
- A major rework and cleanup of the fsl-espi driver from Heiner
Kallweit which should make it work substantially better.
- DMA support for Freescale DSPI IPs.
- New drivers for Freescale LPSPI IPs and Marvell Armada 3700.
- Support for Allwinner H3"
* tag 'spi-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (85 commits)
spi: mvebu: fix baudrate calculation for armada variant
spi: Add support for Armada 3700 SPI Controller
spi: armada-3700: Add documentation for the Armada 3700 SPI Controller
spi: fsl-lpspi: quit reading rx fifo under error condition
spi: fsl-lpspi: use GPL as module license
spi: fsl-espi: fix ioread16/iowrite16 endianness
spi: fsl-espi: remove unused linearization code
spi: fsl-espi: eliminate need for linearization when reading from hardware
spi: fsl-espi: eliminate need for linearization when writing to hardware
spi: fsl-espi: determine need for byte swap only once
spi: fsl-lpspi: read lpspi tx/rx fifo size in probe()
spi: fsl-lpspi: use wait_for_completion_timeout() while waiting transfer done
spi: orion: fix comment to mention MVEBU
spi: atmel: remove the use of private channel fields
spi: atmel: trivial: remove unused fields in DMA structure
spi: atmel: Use SPI core DMA mapping framework
spi: atmel: Use core SPI_MASTER_MUST_[RT]X handling
spi: atmel: trivial: move info banner to latest probe action
spi: imx: replace schedule() with cond_resched()
spi: imx: fix potential shift truncation
...
Diffstat (limited to 'Documentation')
4 files changed, 68 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt b/Documentation/devicetree/bindings/spi/sh-msiof.txt index aa005c1d10d9..da6614c63796 100644 --- a/Documentation/devicetree/bindings/spi/sh-msiof.txt +++ b/Documentation/devicetree/bindings/spi/sh-msiof.txt @@ -10,6 +10,7 @@ Required properties: "renesas,msiof-r8a7792" (R-Car V2H) "renesas,msiof-r8a7793" (R-Car M2-N) "renesas,msiof-r8a7794" (R-Car E2) + "renesas,msiof-r8a7796" (R-Car M3-W) "renesas,msiof-sh73a0" (SH-Mobile AG5) - reg : A list of offsets and lengths of the register sets for the device. diff --git a/Documentation/devicetree/bindings/spi/spi-armada-3700.txt b/Documentation/devicetree/bindings/spi/spi-armada-3700.txt new file mode 100644 index 000000000000..1564aa8c02cd --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-armada-3700.txt @@ -0,0 +1,25 @@ +* Marvell Armada 3700 SPI Controller + +Required Properties: + +- compatible: should be "marvell,armada-3700-spi" +- reg: physical base address of the controller and length of memory mapped + region. +- interrupts: The interrupt number. The interrupt specifier format depends on + the interrupt controller and of its driver. +- clocks: Must contain the clock source, usually from the North Bridge clocks. +- num-cs: The number of chip selects that is supported by this SPI Controller +- #address-cells: should be 1. +- #size-cells: should be 0. + +Example: + + spi0: spi@10600 { + compatible = "marvell,armada-3700-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10600 0x5d>; + clocks = <&nb_perih_clk 7>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + num-cs = <4>; + }; diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt new file mode 100644 index 000000000000..225ace1d0c65 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt @@ -0,0 +1,19 @@ +* Freescale Low Power SPI (LPSPI) for i.MX + +Required properties: +- compatible : + - "fsl,imx7ulp-spi" for LPSPI compatible with the one integrated on i.MX7ULP soc +- reg : address and length of the lpspi master registers +- interrupt-parent : core interrupt controller +- interrupts : lpspi interrupt +- clocks : lpspi clock specifier + +Examples: + +lpspi2: lpspi@40290000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x40290000 0x10000>; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7ULP_CLK_LPSPI2>; +}; diff --git a/Documentation/devicetree/bindings/spi/spi-sun6i.txt b/Documentation/devicetree/bindings/spi/spi-sun6i.txt index 21de73db6a05..2ec99b86b622 100644 --- a/Documentation/devicetree/bindings/spi/spi-sun6i.txt +++ b/Documentation/devicetree/bindings/spi/spi-sun6i.txt @@ -1,7 +1,7 @@ -Allwinner A31 SPI controller +Allwinner A31/H3 SPI controller Required properties: -- compatible: Should be "allwinner,sun6i-a31-spi". +- compatible: Should be "allwinner,sun6i-a31-spi" or "allwinner,sun8i-h3-spi". - reg: Should contain register location and length. - interrupts: Should contain interrupt. - clocks: phandle to the clocks feeding the SPI controller. Two are @@ -12,6 +12,11 @@ Required properties: - resets: phandle to the reset controller asserting this device in reset +Optional properties: +- dmas: DMA specifiers for rx and tx dma. See the DMA client binding, + Documentation/devicetree/bindings/dma/dma.txt +- dma-names: DMA request names should include "rx" and "tx" if present. + Example: spi1: spi@01c69000 { @@ -22,3 +27,19 @@ spi1: spi@01c69000 { clock-names = "ahb", "mod"; resets = <&ahb1_rst 21>; }; + +spi0: spi@01c68000 { + compatible = "allwinner,sun8i-h3-spi"; + reg = <0x01c68000 0x1000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; +}; |