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authorJoel Holdsworth <joel@airwebreathe.org.uk>2017-02-27 16:14:25 -0600
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2017-03-17 15:10:48 +0900
commite10c11d2739fd3657d8d1d5b1fa06f9185b4f012 (patch)
tree92274c80a56e07dc0b5e6892cb0c8648464b1a12 /Documentation
parentf677e0f3ed45a4fcd6270d43b25ff9abb92da608 (diff)
Documentation: Add binding document for Lattice iCE40 FPGA manager
This adds documentation of the device tree bindings of the Lattice iCE40 FPGA driver for the FPGA manager framework. Signed-off-by: Joel Holdsworth <joel@airwebreathe.org.uk> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Alan Tull <atull@opensource.altera.com> Acked-by: Moritz Fischer <moritz.fischer@ettus.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt21
1 files changed, 21 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt
new file mode 100644
index 000000000000..4dc412437b08
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt
@@ -0,0 +1,21 @@
+Lattice iCE40 FPGA Manager
+
+Required properties:
+- compatible: Should contain "lattice,ice40-fpga-mgr"
+- reg: SPI chip select
+- spi-max-frequency: Maximum SPI frequency (>=1000000, <=25000000)
+- cdone-gpios: GPIO input connected to CDONE pin
+- reset-gpios: Active-low GPIO output connected to CRESET_B pin. Note
+ that unless the GPIO is held low during startup, the
+ FPGA will enter Master SPI mode and drive SCK with a
+ clock signal potentially jamming other devices on the
+ bus until the firmware is loaded.
+
+Example:
+ fpga: fpga@0 {
+ compatible = "lattice,ice40-fpga-mgr";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
+ };