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authorJason Gunthorpe <jgunthorpe@obsidianresearch.com>2016-11-21 22:26:45 +0000
committerAlan Tull <atull@opensource.altera.com>2016-11-29 15:51:48 -0600
commit340c0c53ea3073107d5bb7a61f3158e50bf189e0 (patch)
treebdabfcaac67ee4ab224aa5993010ddefbf8ba4db /Documentation/fpga
parent80baf649c2778bb8900cb9011bc712b89faddbdb (diff)
fpga zynq: Fix incorrect ISR state on bootup
It is best practice to clear and mask all interrupts before associating the IRQ, and this should be done after the clock is enabled. This corrects a bad result from zynq_fpga_ops_state on bootup where left over latched values in INT_STS_OFFSET caused it to report an unconfigured FPGA as configured. After this change the boot up operating state for an unconfigured FPGA reports 'unknown'. Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Acked-by: Alan Tull <atull@opensource.altera.com> Acked-by: Moritz Fischer <moritz.fischer@ettus.com>
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