diff options
| author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2014-10-22 11:21:11 +0300 |
|---|---|---|
| committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2014-10-22 11:33:16 +0300 |
| commit | a7f91edfdd009f1a282b9359cf6cd1ef797ced9f (patch) | |
| tree | d61692a2eb6a00b2a61417669e10dd63f0bc36f3 | |
| parent | aba837a280ce9b9be70b172fa8bda3e40a679051 (diff) | |
OMAPDSS: DSI: Fix PLL_SELFEQDCO field width
PLL_SELFREQDCO bitfield is from bit 3 to 1, but the driver writes bits
from 4 to 1. The bit 4 is 'reserved', so this probably should not cause
any issues, but it's better to fix it.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
| -rw-r--r-- | drivers/video/fbdev/omap2/dss/dsi.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/video/fbdev/omap2/dss/dsi.c b/drivers/video/fbdev/omap2/dss/dsi.c index 947bd7b93375..0793bc67a275 100644 --- a/drivers/video/fbdev/omap2/dss/dsi.c +++ b/drivers/video/fbdev/omap2/dss/dsi.c @@ -1603,7 +1603,7 @@ int dsi_pll_set_clock_div(struct platform_device *dsidev, } else if (dss_has_feature(FEAT_DSI_PLL_SELFREQDCO)) { f = cinfo->clkin4ddr < 1000000000 ? 0x2 : 0x4; - l = FLD_MOD(l, f, 4, 1); /* PLL_SELFREQDCO */ + l = FLD_MOD(l, f, 3, 1); /* PLL_SELFREQDCO */ } l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */ |