diff options
| author | Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> | 2017-09-12 21:20:45 +0300 |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2017-10-03 20:36:49 -0700 |
| commit | 976e78a5226598cb582fe9ef98a72861adbc0e9c (patch) | |
| tree | d2fd13138fada059726e766d29a81594fc7ddf5e | |
| parent | 6afa3bcf1f919c374d4606a7ed8078d3f67dfa90 (diff) | |
ARC: [plat-axs10x] sdio: Temporary fix of sdio ciu frequency
DW sdio controller has external ciu clock divider controlled
via register in SDIO IP. It divides sdio_ref_clk
(which comes from CGU) by 16 for default. So default mmcclk
clock (which comes to sdk_in) is 25000000 Hz.
So fix wrong current value (50000000 Hz) to actual 25000000 Hz.
Note this is a preventive fix, in line with similar change for HSDK
where this was actually needed. see:
http://lists.infradead.org/pipermail/linux-snps-arc/2017-September/002924.html
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
| -rw-r--r-- | arch/arc/boot/dts/axs10x_mb.dtsi | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi index 2367a67c5f10..e114000a84f5 100644 --- a/arch/arc/boot/dts/axs10x_mb.dtsi +++ b/arch/arc/boot/dts/axs10x_mb.dtsi @@ -44,7 +44,14 @@ mmcclk: mmcclk { compatible = "fixed-clock"; - clock-frequency = <50000000>; + /* + * DW sdio controller has external ciu clock divider + * controlled via register in SDIO IP. It divides + * sdio_ref_clk (which comes from CGU) by 16 for + * default. So default mmcclk clock (which comes + * to sdk_in) is 25000000 Hz. + */ + clock-frequency = <25000000>; #clock-cells = <0>; }; |