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authorGeert Uytterhoeven <geert@linux-m68k.org>2021-12-17 13:49:32 +0100
committerPalmer Dabbelt <palmer@rivosinc.com>2022-01-09 10:11:44 -0800
commit893eae9ac7e4c23c70874c3981fdcf3311655874 (patch)
treea30afc701c9ce0f8f3105e29927508bb2f16f847
parent8fc6e62a549c61abd594e8435017a31cfca43475 (diff)
riscv: dts: sifive: fu540-c000: Fix PLIC node
Fix the device node for the Platform-Level Interrupt Controller (PLIC): - Add missing "#address-cells" property, - Sort properties according to DT bindings. Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
-rw-r--r--arch/riscv/boot/dts/sifive/fu540-c000.dtsi5
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index b1250c16816f..3eef52b1a59b 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -140,10 +140,10 @@
compatible = "simple-bus";
ranges;
plic0: interrupt-controller@c000000 {
- #interrupt-cells = <1>;
compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
- riscv,ndev = <53>;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
interrupt-controller;
interrupts-extended =
<&cpu0_intc 0xffffffff>,
@@ -151,6 +151,7 @@
<&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
<&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
<&cpu4_intc 0xffffffff>, <&cpu4_intc 9>;
+ riscv,ndev = <53>;
};
prci: clock-controller@10000000 {
compatible = "sifive,fu540-c000-prci";