diff options
| author | Dmitry Osipenko <digetx@gmail.com> | 2019-06-03 21:59:41 +0300 |
|---|---|---|
| committer | Daniel Lezcano <daniel.lezcano@linaro.org> | 2019-06-25 19:49:18 +0200 |
| commit | 77d57d1d8016696daaf5614c070ac01c9652f4ce (patch) | |
| tree | 699922341a82a4f3191ff08f9f65f4022d151a89 | |
| parent | af8d9129eced348c699cca73b1c52e3855df063e (diff) | |
clocksource/drivers/tegra: Reset hardware state on init
Reset timer's hardware state to ensure that initially it is in a
predictable state.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| -rw-r--r-- | drivers/clocksource/timer-tegra20.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index acd68c77fa91..3e4f12aee8df 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -123,6 +123,9 @@ static int tegra_timer_setup(unsigned int cpu) { struct timer_of *to = per_cpu_ptr(&tegra_to, cpu); + writel(0, timer_of_base(to) + TIMER_PTV); + writel(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR); + irq_force_affinity(to->clkevt.irq, cpumask_of(cpu)); enable_irq(to->clkevt.irq); |