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| author | Will Deacon <will@kernel.org> | 2022-03-14 19:00:37 +0000 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2022-03-14 19:00:37 +0000 |
| commit | b523d6b80fbcf45f64f5010424a273c32df79e7a (patch) | |
| tree | dae20ed70ed7e5c6d963f9b776e4512d973605b9 | |
| parent | 0d3d031595cbac3d57a68e600a7facab1ecbdece (diff) | |
| parent | 4c022f57ad954e1ad6f838bd3b7d54e459745eeb (diff) | |
Merge branch 'for-next/docs' into for-next/core
* for-next/docs:
arm64/mte: Clarify mode reported by PR_GET_TAGGED_ADDR_CTRL
arm64: booting.rst: Clarify on requiring non-secure EL2
| -rw-r--r-- | Documentation/arm64/booting.rst | 10 | ||||
| -rw-r--r-- | Documentation/arm64/memory-tagging-extension.rst | 5 |
2 files changed, 8 insertions, 7 deletions
diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst index 52d060caf8bb..29884b261aa9 100644 --- a/Documentation/arm64/booting.rst +++ b/Documentation/arm64/booting.rst @@ -10,9 +10,9 @@ This document is based on the ARM booting document by Russell King and is relevant to all public releases of the AArch64 Linux kernel. The AArch64 exception model is made up of a number of exception levels -(EL0 - EL3), with EL0 and EL1 having a secure and a non-secure -counterpart. EL2 is the hypervisor level and exists only in non-secure -mode. EL3 is the highest priority level and exists only in secure mode. +(EL0 - EL3), with EL0, EL1 and EL2 having a secure and a non-secure +counterpart. EL2 is the hypervisor level, EL3 is the highest priority +level and exists only in secure mode. Both are architecturally optional. For the purposes of this document, we will use the term `boot loader` simply to define all software that executes on the CPU(s) before control @@ -167,8 +167,8 @@ Before jumping into the kernel, the following conditions must be met: All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError, IRQ and FIQ). - The CPU must be in either EL2 (RECOMMENDED in order to have access to - the virtualisation extensions) or non-secure EL1. + The CPU must be in non-secure state, either in EL2 (RECOMMENDED in order + to have access to the virtualisation extensions), or in EL1. - Caches, MMUs diff --git a/Documentation/arm64/memory-tagging-extension.rst b/Documentation/arm64/memory-tagging-extension.rst index 5a70d7a3ca12..6ccbdc408df6 100644 --- a/Documentation/arm64/memory-tagging-extension.rst +++ b/Documentation/arm64/memory-tagging-extension.rst @@ -91,8 +91,9 @@ mode is specified, the program will run in that mode. If multiple modes are specified, the mode is selected as described in the "Per-CPU preferred tag checking modes" section below. -The current tag check fault mode can be read using the -``prctl(PR_GET_TAGGED_ADDR_CTRL, 0, 0, 0, 0)`` system call. +The current tag check fault configuration can be read using the +``prctl(PR_GET_TAGGED_ADDR_CTRL, 0, 0, 0, 0)`` system call. If +multiple modes were requested then all will be reported. Tag checking can also be disabled for a user thread by setting the ``PSTATE.TCO`` bit with ``MSR TCO, #1``. |