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authorAndrew Lunn <andrew@lunn.ch>2016-11-10 15:44:01 +0100
committerDavid S. Miller <davem@davemloft.net>2016-11-13 22:36:35 -0500
commit94d66ae63151ab8db47fe468f5fe37a616f7bfeb (patch)
tree9f6b2fedc17e9e8804dfefb5dded2b2307ed87fe
parentfedf18651b07f1701f9e8684b49f3b6c879577fc (diff)
net: dsa: mv88e6xxx: 6351 family also has RGMII delays
The recent refactoring of setting the MAC configuration broke setting of RGMII delays, via the phy-mode, on the 6351 family. Add the missing ops to the structure. Fixes: 7340e5ecdbb1 ("net: dsa: mv88e6xxx: setup port's MAC") Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/dsa/mv88e6xxx/chip.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index c8f824d4ff26..d6d9d66b81ce 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -3196,6 +3196,7 @@ static const struct mv88e6xxx_ops mv88e6171_ops = {
.phy_write = mv88e6xxx_g2_smi_phy_write,
.port_set_link = mv88e6xxx_port_set_link,
.port_set_duplex = mv88e6xxx_port_set_duplex,
+ .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
.port_set_speed = mv88e6185_port_set_speed,
};
@@ -3217,6 +3218,7 @@ static const struct mv88e6xxx_ops mv88e6175_ops = {
.phy_write = mv88e6xxx_g2_smi_phy_write,
.port_set_link = mv88e6xxx_port_set_link,
.port_set_duplex = mv88e6xxx_port_set_duplex,
+ .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
.port_set_speed = mv88e6185_port_set_speed,
};
@@ -3281,6 +3283,7 @@ static const struct mv88e6xxx_ops mv88e6350_ops = {
.phy_write = mv88e6xxx_g2_smi_phy_write,
.port_set_link = mv88e6xxx_port_set_link,
.port_set_duplex = mv88e6xxx_port_set_duplex,
+ .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
.port_set_speed = mv88e6185_port_set_speed,
};
@@ -3290,6 +3293,7 @@ static const struct mv88e6xxx_ops mv88e6351_ops = {
.phy_write = mv88e6xxx_g2_smi_phy_write,
.port_set_link = mv88e6xxx_port_set_link,
.port_set_duplex = mv88e6xxx_port_set_duplex,
+ .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
.port_set_speed = mv88e6185_port_set_speed,
};