diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2023-03-03 09:32:51 -0800 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2023-03-03 09:32:51 -0800 |
commit | bf1a1bad82407ad81130c065f6495ec0f939ae60 (patch) | |
tree | 1067a74a84186de39a94dd1e1ff6faae6c8ebe36 | |
parent | 271d89394e33aae5391fd886c046ce54c8240e5b (diff) | |
parent | 61fc1ee8be26bc192d691932b0a67eabee45d12f (diff) |
Merge tag 'riscv-for-linus-6.3-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull more RISC-V updates from Palmer Dabbelt:
- Some cleanups and fixes for the Zbb-optimized string routines
- Support for custom (vendor or implementation defined) perf events
- COMMAND_LINE_SIZE has been increased to 1024
* tag 'riscv-for-linus-6.3-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: Bump COMMAND_LINE_SIZE value to 1024
drivers/perf: RISC-V: Allow programming custom firmware events
riscv, lib: Fix Zbb strncmp
RISC-V: improve string-function assembly
-rw-r--r-- | arch/riscv/include/uapi/asm/setup.h | 8 | ||||
-rw-r--r-- | arch/riscv/lib/strcmp.S | 6 | ||||
-rw-r--r-- | arch/riscv/lib/strlen.S | 10 | ||||
-rw-r--r-- | arch/riscv/lib/strncmp.S | 20 | ||||
-rw-r--r-- | drivers/perf/riscv_pmu_sbi.c | 7 |
5 files changed, 29 insertions, 22 deletions
diff --git a/arch/riscv/include/uapi/asm/setup.h b/arch/riscv/include/uapi/asm/setup.h new file mode 100644 index 000000000000..66b13a522880 --- /dev/null +++ b/arch/riscv/include/uapi/asm/setup.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ + +#ifndef _UAPI_ASM_RISCV_SETUP_H +#define _UAPI_ASM_RISCV_SETUP_H + +#define COMMAND_LINE_SIZE 1024 + +#endif /* _UAPI_ASM_RISCV_SETUP_H */ diff --git a/arch/riscv/lib/strcmp.S b/arch/riscv/lib/strcmp.S index 986ab23fe787..c42a8412547f 100644 --- a/arch/riscv/lib/strcmp.S +++ b/arch/riscv/lib/strcmp.S @@ -40,7 +40,9 @@ SYM_FUNC_START(strcmp) ret /* - * Variant of strcmp using the ZBB extension if available + * Variant of strcmp using the ZBB extension if available. + * The code was published as part of the bitmanip manual + * in Appendix A. */ #ifdef CONFIG_RISCV_ISA_ZBB strcmp_zbb: @@ -57,7 +59,7 @@ strcmp_zbb: * a1 - string2 * * Clobbers - * t0, t1, t2, t3, t4, t5 + * t0, t1, t2, t3, t4 */ or t2, a0, a1 diff --git a/arch/riscv/lib/strlen.S b/arch/riscv/lib/strlen.S index 8345ceeee3f6..15bb8f3aa959 100644 --- a/arch/riscv/lib/strlen.S +++ b/arch/riscv/lib/strlen.S @@ -96,7 +96,7 @@ strlen_zbb: * of valid bytes in this chunk. */ srli a0, t1, 3 - bgtu t3, a0, 3f + bgtu t3, a0, 2f /* Prepare for the word comparison loop. */ addi t2, t0, SZREG @@ -112,20 +112,20 @@ strlen_zbb: addi t0, t0, SZREG orc.b t1, t1 beq t1, t3, 1b -2: + not t1, t1 CZ t1, t1 + srli t1, t1, 3 - /* Get number of processed words. */ + /* Get number of processed bytes. */ sub t2, t0, t2 /* Add number of characters in the first word. */ add a0, a0, t2 - srli t1, t1, 3 /* Add number of characters in the last word. */ add a0, a0, t1 -3: +2: ret .option pop diff --git a/arch/riscv/lib/strncmp.S b/arch/riscv/lib/strncmp.S index ee49595075be..7ac2f667285a 100644 --- a/arch/riscv/lib/strncmp.S +++ b/arch/riscv/lib/strncmp.S @@ -70,7 +70,7 @@ strncmp_zbb: li t5, -1 and t2, t2, SZREG-1 add t4, a0, a2 - bnez t2, 4f + bnez t2, 3f /* Adjust limit for fast-path. */ andi t6, t4, -SZREG @@ -78,11 +78,13 @@ strncmp_zbb: /* Main loop for aligned string. */ .p2align 3 1: - bgt a0, t6, 3f + bge a0, t6, 3f REG_L t0, 0(a0) REG_L t1, 0(a1) orc.b t3, t0 bne t3, t5, 2f + orc.b t3, t1 + bne t3, t5, 2f addi a0, a0, SZREG addi a1, a1, SZREG beq t0, t1, 1b @@ -114,23 +116,21 @@ strncmp_zbb: ret /* Simple loop for misaligned strings. */ -3: - /* Restore limit for slow-path. */ .p2align 3 -4: - bge a0, t4, 6f +3: + bge a0, t4, 5f lbu t0, 0(a0) lbu t1, 0(a1) addi a0, a0, 1 addi a1, a1, 1 - bne t0, t1, 5f - bnez t0, 4b + bne t0, t1, 4f + bnez t0, 3b -5: +4: sub a0, t0, t1 ret -6: +5: li a0, 0 ret diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index c9116d9e4b57..70cb50fd41c2 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -436,11 +436,8 @@ static int pmu_sbi_event_map(struct perf_event *event, u64 *econfig) bSoftware = config >> 63; raw_config_val = config & RISCV_PMU_RAW_EVENT_MASK; if (bSoftware) { - if (raw_config_val < SBI_PMU_FW_MAX) - ret = (raw_config_val & 0xFFFF) | - (SBI_PMU_EVENT_TYPE_FW << 16); - else - return -EINVAL; + ret = (raw_config_val & 0xFFFF) | + (SBI_PMU_EVENT_TYPE_FW << 16); } else { ret = RISCV_PMU_RAW_EVENT_IDX; *econfig = raw_config_val; |