diff options
| author | Andrew Isaacson <adi@broadcom.com> | 2005-10-19 23:54:43 -0700 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 19:32:45 +0100 |
| commit | d121ced21d79eab7726bfe6b1e33da4ae86072c0 (patch) | |
| tree | a673fe4d3e3c49179b68c3185ef331712df9e716 | |
| parent | 485a4a928a059a361c7363e7ce0eab330a09dbd3 (diff) | |
Sibyte fixes
Fix typo in cpu_probe_sibyte.
Signed-Off-By: Andy Isaacson <adi@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/kernel/cpu-probe.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 72c580d94e24..f7a841573b84 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -612,7 +612,7 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c) * cache code which eventually will be folded into c-r4k.c. Until * then we pretend it's got it's own cache architecture. */ - c->options &= MIPS_CPU_4K_CACHE; + c->options &= ~MIPS_CPU_4K_CACHE; c->options |= MIPS_CPU_SB1_CACHE; switch (c->processor_id & 0xff00) { |