diff options
| author | Joakim Zhang <qiangqing.zhang@nxp.com> | 2020-02-25 20:56:43 +0800 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2020-03-02 12:07:19 +0000 |
| commit | 049d919168458ac54e7fad27cd156a958b042d2f (patch) | |
| tree | 7a1fa34cf4825d70c3bbdef0c9b9d6760f0abe75 | |
| parent | dcde237319e626d1ec3c9d8b7613032f0fd4663a (diff) | |
drivers/perf: fsl_imx8_ddr: Correct the CLEAR bit definition
When disabling a counter from ddr_perf_event_stop(), the counter value
is reset to 0 at the same time.
Preserve the counter value by performing a read-modify-write of the
PMU register and clearing only the enable bit.
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: Will Deacon <will@kernel.org>
| -rw-r--r-- | drivers/perf/fsl_imx8_ddr_perf.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c index 95dca2cb5265..90884d14f95f 100644 --- a/drivers/perf/fsl_imx8_ddr_perf.c +++ b/drivers/perf/fsl_imx8_ddr_perf.c @@ -388,9 +388,10 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, if (enable) { /* - * must disable first, then enable again - * otherwise, cycle counter will not work - * if previous state is enabled. + * cycle counter is special which should firstly write 0 then + * write 1 into CLEAR bit to clear it. Other counters only + * need write 0 into CLEAR bit and it turns out to be 1 by + * hardware. Below enable flow is harmless for all counters. */ writel(0, pmu->base + reg); val = CNTL_EN | CNTL_CLEAR; @@ -398,7 +399,8 @@ static void ddr_perf_counter_enable(struct ddr_pmu *pmu, int config, writel(val, pmu->base + reg); } else { /* Disable counter */ - writel(0, pmu->base + reg); + val = readl_relaxed(pmu->base + reg) & CNTL_EN_MASK; + writel(val, pmu->base + reg); } } |