diff options
| author | James Hogan <james.hogan@imgtec.com> | 2015-12-16 23:49:34 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2016-01-24 03:20:46 +0100 |
| commit | 044c9bb816433c196a5776ac4834c23eced205e7 (patch) | |
| tree | 5a9f5f12a807cfbe049c5ce9422b38eb362ba4d5 | |
| parent | 16d100db245ab34d975e080f39e4cc4ed09b3820 (diff) | |
MIPS: Update trap codes
Add a few missing trap codes.
[ralf@linux-mips.org: Drop removal of exception codes. I don't care what
the incomplete architecture spec says; it can't change existing hardware
and VCEI is supported indeed.]
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Gleb Natapov <gleb@kernel.org>
Cc: kvm@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/11890/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/include/asm/mipsregs.h | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index eb89b877c6c9..3ad19ad04d8a 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -420,12 +420,20 @@ #define EXCCODE_CPU 11 /* Coprocessor unusable */ #define EXCCODE_OV 12 /* Arithmetic overflow */ #define EXCCODE_TR 13 /* Trap instruction */ -#define EXCCODE_VCEI 14 /* Virtual coherency exception */ #define EXCCODE_MSAFPE 14 /* MSA floating point exception */ #define EXCCODE_FPE 15 /* Floating point exception */ +#define EXCCODE_TLBRI 19 /* TLB Read-Inhibit exception */ +#define EXCCODE_TLBXI 20 /* TLB Execution-Inhibit exception */ #define EXCCODE_MSADIS 21 /* MSA disabled exception */ +#define EXCCODE_MDMX 22 /* MDMX unusable exception */ #define EXCCODE_WATCH 23 /* Watch address reference */ -#define EXCCODE_VCED 31 /* Virtual coherency data */ +#define EXCCODE_MCHECK 24 /* Machine check */ +#define EXCCODE_THREAD 25 /* Thread exceptions (MT) */ +#define EXCCODE_DSPDIS 26 /* DSP disabled exception */ +#define EXCCODE_GE 27 /* Virtualized guest exception (VZ) */ + +/* Implementation specific trap codes used by MIPS cores */ +#define MIPS_EXCCODE_TLBPAR 16 /* TLB parity error exception */ /* * Bits in the coprocessor 0 config register. |