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authorKenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>2011-11-10 16:42:16 +0900
committerJesse Barnes <jbarnes@virtuousgeek.org>2011-11-11 09:31:43 -0800
commitb3c004542229099e18198061c737e13eafc8d4d6 (patch)
treea9c753784797cb2252e5386cc128aeff3ab23ceb
parent0027cb3e1947d0f453fece40ed16764fb362bac6 (diff)
PCI: pciehp: wait 100 ms after Link Training check
If the port supports Link speeds greater than 5.0 GT/s, we must wait for 100 ms after Link training completes before sending configuration request. Acked-by: Yinghai Lu <yinghai@kernel.org> Tested-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
-rw-r--r--drivers/pci/hotplug/pciehp_hpc.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c
index 81a177a5f032..7b1414810ae3 100644
--- a/drivers/pci/hotplug/pciehp_hpc.c
+++ b/drivers/pci/hotplug/pciehp_hpc.c
@@ -302,6 +302,14 @@ int pciehp_check_link_status(struct controller *ctrl)
return retval;
}
+ /*
+ * If the port supports Link speeds greater than 5.0 GT/s, we
+ * must wait for 100 ms after Link training completes before
+ * sending configuration request.
+ */
+ if (ctrl->pcie->port->subordinate->max_bus_speed > PCIE_SPEED_5_0GT)
+ msleep(100);
+
pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
return retval;