diff options
| author | Matt Carlson <mcarlson@broadcom.com> | 2009-04-20 06:57:41 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2009-04-21 01:41:01 -0700 |
| commit | 33466d938f43ab65312466ba5472b9c6ee200cce (patch) | |
| tree | a84a6f6de32b2269006e70f5d4d04732940c8746 | |
| parent | df259d8cba7d7880dc04d34c7a6e0ce15fbc9644 (diff) | |
tg3: Prevent send BD corruption
On rare occasions, send BD corruptions can occur. This patch
fixes the problem by increasing the L1 entry threshold to 4
milliseconds.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
| -rw-r--r-- | drivers/net/tg3.c | 7 | ||||
| -rw-r--r-- | drivers/net/tg3.h | 2 |
2 files changed, 9 insertions, 0 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 9b04954b6943..ed7a86df98cd 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -6717,6 +6717,13 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) tw32(TG3_CPMU_HST_ACC, val); } + if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) { + val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK; + val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN | + PCIE_PWR_MGMT_L1_THRESH_4MS; + tw32(PCIE_PWR_MGMT_THRESH, val); + } + /* This works around an issue with Athlon chipsets on * B3 tigon3 silicon. This bit has no effect on any * other revision. But do not set this on PCI Express diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index afbabf283c51..f1016cb1a89a 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h @@ -1697,6 +1697,8 @@ #define PCIE_PWR_MGMT_THRESH 0x00007d28 #define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00 +#define PCIE_PWR_MGMT_L1_THRESH_4MS 0x0000ff00 +#define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN 0x01000000 /* OTP bit definitions */ |