diff options
| author | Grant Grundler <grundler@parisc-linux.org> | 2006-09-08 11:15:37 -0700 |
|---|---|---|
| committer | Jeff Garzik <jeff@garzik.org> | 2006-09-11 09:05:37 -0400 |
| commit | 40c0d87948ab635e814f45664259d4cc193651a1 (patch) | |
| tree | 24c3c8e62eef0db500466540a7338d161c7ce5d7 | |
| parent | b892de0bd79d534ff4dcbae7aa2ad5b63e23e9fd (diff) | |
[PATCH] Flush MMIO writes in reset sequence
The obvious safe registers to read is one from PCI config space.
Signed-off-by: Grant Grundler <grundler@parisc-linux.org>
Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
Signed-off-by: Valerie Henson <val_henson@linux.intel.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
| -rw-r--r-- | drivers/net/tulip/tulip_core.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/net/tulip/tulip_core.c b/drivers/net/tulip/tulip_core.c index 2f181809bde2..6a7ca8695ff2 100644 --- a/drivers/net/tulip/tulip_core.c +++ b/drivers/net/tulip/tulip_core.c @@ -295,12 +295,14 @@ static void tulip_up(struct net_device *dev) /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */ iowrite32(0x00000001, ioaddr + CSR0); + pci_read_config_dword(tp->pdev, PCI_COMMAND, &i); /* flush write */ udelay(100); /* Deassert reset. Wait the specified 50 PCI cycles after a reset by initializing Tx and Rx queues and the address filter list. */ iowrite32(tp->csr0, ioaddr + CSR0); + pci_read_config_dword(tp->pdev, PCI_COMMAND, &i); /* flush write */ udelay(100); if (tulip_debug > 1) |