diff options
| author | Alexander Duyck <alexander.h.duyck@intel.com> | 2009-10-05 06:36:01 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2009-10-06 14:59:24 -0700 |
| commit | 6deac6f2b46f84b8822683cce92eab4edf2ade5e (patch) | |
| tree | 9423486a368aec154279e7624f1c1fbd6c61b657 | |
| parent | 2553bb2681645bf932db2845121b8f33954f6f39 (diff) | |
igb: add flushes between RAR writes when setting mac address
There are some switches that will do write combining when they see two
sequential regions written. In order to avoid any possible write combining
issues it is necessary to add a flush after writing each piece of a rar
register.
Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
| -rw-r--r-- | drivers/net/igb/e1000_mac.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/net/igb/e1000_mac.c b/drivers/net/igb/e1000_mac.c index 4969a5b1cf3c..2ad358a240bf 100644 --- a/drivers/net/igb/e1000_mac.c +++ b/drivers/net/igb/e1000_mac.c @@ -247,8 +247,15 @@ void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) if (rar_low || rar_high) rar_high |= E1000_RAH_AV; + /* + * Some bridges will combine consecutive 32-bit writes into + * a single burst write, which will malfunction on some parts. + * The flushes avoid this. + */ wr32(E1000_RAL(index), rar_low); + wrfl(); wr32(E1000_RAH(index), rar_high); + wrfl(); } /** |