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authorBen Widawsky <benjamin.widawsky@intel.com>2014-05-06 22:21:36 -0700
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-05-07 10:01:41 +0200
commit6e7186af3b815adda710ee8b4a6f1402776661c0 (patch)
treea52a63c9c402325ca0f1e6afe14ccf6f54b6bcb9
parent3e8b5ae9b0e48281712ade208a2d0d6d2ee4a6d6 (diff)
drm/i915: Make aliasing a 2nd class VM
There is a good debate to be had about how best to fit the aliasing PPGTT into the code. However, as it stands right now, getting aliasing PPGTT bindings is a hack, and done through implicit arguments. To make this absolutely clear, WARN and return an error if a driver writer tries to do something they shouldn't. I have no issue with an eventual revert of this patch. It makes sense for what we have today. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e1fa919017e2..8fd18246a158 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3852,9 +3852,13 @@ i915_gem_object_pin(struct drm_i915_gem_object *obj,
uint32_t alignment,
unsigned flags)
{
+ struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
struct i915_vma *vma;
int ret;
+ if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
+ return -ENODEV;
+
if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
return -EINVAL;