Merge tag 'asahi-soc-dt-6.2-v3' of https://github.com/AsahiLinux/linux into soc/dt

Apple SoC DT updates for 6.2 (v3).

One final update for 6.2. This includes:
* L1/L2 cache topology for t8103
* A bunch of typo, style, and minor functional fixes

* tag 'asahi-soc-dt-6.2-v3' of https://github.com/AsahiLinux/linux:
  arm64: dts: apple: t6002: Fix GPU power domains
  arm64: dts: apple: t600x-pmgr: Fix search & replace typo
  arm64: dts: apple: Add t8103 L1/L2 cache properties and nodes
  arm64: dts: apple: Rename dart-sio* to sio-dart*
  arch: arm64: apple: t600x: Use standard "iommu" node name
  arch: arm64: apple: t8103: Use standard "iommu" node name

Link: https://lore.kernel.org/r/488ad4e9-04dc-1774-3bbe-d313ef30f14d@marcan.st
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

4 files changed, 56 insertions, 13 deletions

diff --git a/arch/arm64/boot/dts/apple/t6002.dtsi b/arch/arm64/boot/dts/apple/t6002.dtsi
index 15da2c7eb1fe..a963a5011799 100644
--- a/arch/arm64/boot/dts/apple/t6002.dtsi
+++ b/arch/arm64/boot/dts/apple/t6002.dtsi
@@ -294,3 +294,8 @@
 		};
 	};
 };
+
+&ps_gfx {
+	// On t6002, the die0 GPU power domain needs both AFR power domains
+	power-domains = <&ps_afr>, <&ps_afr_die1>;
+};
diff --git a/arch/arm64/boot/dts/apple/t600x-die0.dtsi b/arch/arm64/boot/dts/apple/t600x-die0.dtsi
index 0b8958a8db77..1c41954e3899 100644
--- a/arch/arm64/boot/dts/apple/t600x-die0.dtsi
+++ b/arch/arm64/boot/dts/apple/t600x-die0.dtsi
@@ -53,7 +53,7 @@
 		interrupts = <AIC_IRQ 0 631 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
-	dart_sio_0: iommu@39b004000 {
+	sio_dart_0: iommu@39b004000 {
 		compatible = "apple,t6000-dart";
 		reg = <0x3 0x9b004000 0x0 0x4000>;
 		interrupt-parent = <&aic>;
@@ -62,7 +62,7 @@
 		power-domains = <&ps_sio_cpu>;
 	};
 
-	dart_sio_1: iommu@39b008000 {
+	sio_dart_1: iommu@39b008000 {
 		compatible = "apple,t6000-dart";
 		reg = <0x3 0x9b008000 0x0 0x8000>;
 		interrupt-parent = <&aic>;
@@ -179,7 +179,7 @@
 				      <&aic AIC_IRQ 0 1118 IRQ_TYPE_LEVEL_HIGH>,
 				      <0>,
 				      <0>;
-		iommus = <&dart_sio_0 2>, <&dart_sio_1 2>;
+		iommus = <&sio_dart_0 2>, <&sio_dart_1 2>;
 		power-domains = <&ps_sio_adma>;
 		resets = <&ps_audio_p>;
 	};
@@ -208,7 +208,7 @@
 		#sound-dai-cells = <1>;
 	};
 
-	pcie0_dart_0: dart@581008000 {
+	pcie0_dart_0: iommu@581008000 {
 		compatible = "apple,t6000-dart";
 		reg = <0x5 0x81008000 0x0 0x4000>;
 		#iommu-cells = <1>;
@@ -217,7 +217,7 @@
 		power-domains = <&ps_apcie_gp_sys>;
 	};
 
-	pcie0_dart_1: dart@582008000 {
+	pcie0_dart_1: iommu@582008000 {
 		compatible = "apple,t6000-dart";
 		reg = <0x5 0x82008000 0x0 0x4000>;
 		#iommu-cells = <1>;
@@ -226,7 +226,7 @@
 		power-domains = <&ps_apcie_gp_sys>;
 	};
 
-	pcie0_dart_2: dart@583008000 {
+	pcie0_dart_2: iommu@583008000 {
 		compatible = "apple,t6000-dart";
 		reg = <0x5 0x83008000 0x0 0x4000>;
 		#iommu-cells = <1>;
@@ -235,7 +235,7 @@
 		power-domains = <&ps_apcie_gp_sys>;
 	};
 
-	pcie0_dart_3: dart@584008000 {
+	pcie0_dart_3: iommu@584008000 {
 		compatible = "apple,t6000-dart";
 		reg = <0x5 0x84008000 0x0 0x4000>;
 		#iommu-cells = <1>;
diff --git a/arch/arm64/boot/dts/apple/t600x-pmgr.dtsi b/arch/arm64/boot/dts/apple/t600x-pmgr.dtsi
index b8daeb0368d5..0bd44753b76a 100644
--- a/arch/arm64/boot/dts/apple/t600x-pmgr.dtsi
+++ b/arch/arm64/boot/dts/apple/t600x-pmgr.dtsi
@@ -225,7 +225,7 @@
 		#power-domain-cells = <0>;
 		#reset-cells = <0>;
 		label = DIE_LABEL(afr);
-		/* Apple Fabric, media DIE_NODE(stuff): this can power down */
+		/* Apple Fabric, media stuff: this can power down */
 	};
 
 	DIE_NODE(ps_afnc1_ioa): power-controller@1f0 {
diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi
index 6f5a2334e5b1..9859219699f4 100644
--- a/arch/arm64/boot/dts/apple/t8103.dtsi
+++ b/arch/arm64/boot/dts/apple/t8103.dtsi
@@ -63,6 +63,9 @@
 			operating-points-v2 = <&ecluster_opp>;
 			capacity-dmips-mhz = <714>;
 			performance-domains = <&cpufreq_e>;
+			next-level-cache = <&l2_cache_0>;
+			i-cache-size = <0x20000>;
+			d-cache-size = <0x10000>;
 		};
 
 		cpu_e1: cpu@1 {
@@ -74,6 +77,9 @@
 			operating-points-v2 = <&ecluster_opp>;
 			capacity-dmips-mhz = <714>;
 			performance-domains = <&cpufreq_e>;
+			next-level-cache = <&l2_cache_0>;
+			i-cache-size = <0x20000>;
+			d-cache-size = <0x10000>;
 		};
 
 		cpu_e2: cpu@2 {
@@ -85,6 +91,9 @@
 			operating-points-v2 = <&ecluster_opp>;
 			capacity-dmips-mhz = <714>;
 			performance-domains = <&cpufreq_e>;
+			next-level-cache = <&l2_cache_0>;
+			i-cache-size = <0x20000>;
+			d-cache-size = <0x10000>;
 		};
 
 		cpu_e3: cpu@3 {
@@ -96,6 +105,9 @@
 			operating-points-v2 = <&ecluster_opp>;
 			capacity-dmips-mhz = <714>;
 			performance-domains = <&cpufreq_e>;
+			next-level-cache = <&l2_cache_0>;
+			i-cache-size = <0x20000>;
+			d-cache-size = <0x10000>;
 		};
 
 		cpu_p0: cpu@10100 {
@@ -107,6 +119,9 @@
 			operating-points-v2 = <&pcluster_opp>;
 			capacity-dmips-mhz = <1024>;
 			performance-domains = <&cpufreq_p>;
+			next-level-cache = <&l2_cache_1>;
+			i-cache-size = <0x30000>;
+			d-cache-size = <0x20000>;
 		};
 
 		cpu_p1: cpu@10101 {
@@ -118,6 +133,9 @@
 			operating-points-v2 = <&pcluster_opp>;
 			capacity-dmips-mhz = <1024>;
 			performance-domains = <&cpufreq_p>;
+			next-level-cache = <&l2_cache_1>;
+			i-cache-size = <0x30000>;
+			d-cache-size = <0x20000>;
 		};
 
 		cpu_p2: cpu@10102 {
@@ -129,6 +147,9 @@
 			operating-points-v2 = <&pcluster_opp>;
 			capacity-dmips-mhz = <1024>;
 			performance-domains = <&cpufreq_p>;
+			next-level-cache = <&l2_cache_1>;
+			i-cache-size = <0x30000>;
+			d-cache-size = <0x20000>;
 		};
 
 		cpu_p3: cpu@10103 {
@@ -140,6 +161,23 @@
 			operating-points-v2 = <&pcluster_opp>;
 			capacity-dmips-mhz = <1024>;
 			performance-domains = <&cpufreq_p>;
+			next-level-cache = <&l2_cache_1>;
+			i-cache-size = <0x30000>;
+			d-cache-size = <0x20000>;
+		};
+
+		l2_cache_0: l2-cache-0 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-unified;
+			cache-size = <0x400000>;
+		};
+
+		l2_cache_1: l2-cache-1 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-unified;
+			cache-size = <0xc00000>;
 		};
 	};
 
@@ -318,7 +356,7 @@
 			#performance-domain-cells = <0>;
 		};
 
-		dart_sio: iommu@235004000 {
+		sio_dart: iommu@235004000 {
 			compatible = "apple,t8103-dart";
 			reg = <0x2 0x35004000 0x0 0x4000>;
 			interrupt-parent = <&aic>;
@@ -431,7 +469,7 @@
 					      <0>,
 					      <0>;
 			#dma-cells = <1>;
-			iommus = <&dart_sio 2>;
+			iommus = <&sio_dart 2>;
 			power-domains = <&ps_sio_adma>;
 			resets = <&ps_audio_p>;
 		};
@@ -670,7 +708,7 @@
 			resets = <&ps_ans2>;
 		};
 
-		pcie0_dart_0: dart@681008000 {
+		pcie0_dart_0: iommu@681008000 {
 			compatible = "apple,t8103-dart";
 			reg = <0x6 0x81008000 0x0 0x4000>;
 			#iommu-cells = <1>;
@@ -679,7 +717,7 @@
 			power-domains = <&ps_apcie_gp>;
 		};
 
-		pcie0_dart_1: dart@682008000 {
+		pcie0_dart_1: iommu@682008000 {
 			compatible = "apple,t8103-dart";
 			reg = <0x6 0x82008000 0x0 0x4000>;
 			#iommu-cells = <1>;
@@ -688,7 +726,7 @@
 			power-domains = <&ps_apcie_gp>;
 		};
 
-		pcie0_dart_2: dart@683008000 {
+		pcie0_dart_2: iommu@683008000 {
 			compatible = "apple,t8103-dart";
 			reg = <0x6 0x83008000 0x0 0x4000>;
 			#iommu-cells = <1>;